library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 

entity clock is
    Port ( clk : out STD_LOGIC );
end entity;

architecture Behavioral of clock is
    
begin
    process
    begin
        while true loop
	    clk <= '0';
	    wait for 5 ns;   
            clk <= '1';
            wait for 5 ns;       
        end loop;
    end process;
 
end architecture Behavioral;
